Event Date/Time: Mar 26, 2001 End Date/Time: Mar 28, 2001
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With the increasing complexity of VLSI systems, hardware testability structures are becoming more commonplace. Advances in technology have enabled systems on chips, and Design for Testability (DFT) is necessary to handle such complex designs. Design reuse is an important issue for many designers, and ensuring testability of designs that use IP cores is essential. While ad-hoc DFT techniques have been used in the past, automatic synthesis of DFT hardware has become necessary in many design environments. This workshop discusses all aspects of Test Synthesis, loosely defined as the enabling technology of Design for Test. The topics include, but are not limited to, the following:

Register Transfer Level DFT
High-Level/Behavioral Test Synthesis
System on Chip Design for Test
Synthesis of BIST Hardware
Synthesis of Test Access Structures
Test Synthesis for Mixed Signal Circuits
Test Synthesis for Programmable Structures
Test Scheduling
Test Synthesis to reduce test cost