DTVCS 2008 - Design, Testing and Formal Verification Techniques for Integrated Circuits and Systems (DTVCS 2008)
Venue: Kailua-Kona
Location: Kailua-Kona, United States
Event Date/Time: Aug 18, 2008 | End Date/Time: Aug 20, 2008 |
Paper Submission Date: Apr 01, 2008 |
Description
computer scientists, practitioners and people from industry to exchange theories, ideas,
techniques and experiences related to the areas of design, testing and formal verification techniques
for integrated circuits and systems. Contributions on UML and formal paradigms based on process algebras,
petri-nets, automaton theory and BDDs in the context of design, testing and formal verification techniques
for integrated circuits and systems are also encouraged.